TS-MAC-XM-UT4【PDF 5/66 页】SITE LICENSE ETH MAC TRI-SPD XP

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Chapter 1:

Introduction

This document provides technical information about the Lattice 10/100/1G Tri-Speed Ethernet Media Access Con-

troller (TSMAC) IP core.

The TSMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet

network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3

IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC

extracts the different components of a frame and transfers them to higher applications through the FIFO interface.

The TSMAC IP core comes with the following documentation and files:

? Protected netlist/database

? Behavioral RTL simulation model

? Source files for instantiating and evaluating the core

Quick Facts

Table 1-1 gives quick facts about the TSMAC IP core.

Table 1-1. TSMAC IP Core Quick Facts

TSMAC IP Configuration

Across all configuration options (Classic, Gigabit, SGMII, MIIM) 1

Core

FPGA Families

Supported

LatticeEC TM

Lattice ECP TM

Lattice ECP2 TM LatticeECP2M TM LatticeECP3 TM LatticeXP TM

LatticeXP2 TM

LatticeSC TM

LatticeSCM

Requirements

Minimal Device

Needed

Data Path Width

LFEC3E-

5F100C

8

LFE2-6E-

5F144CES

8

LFE2M20-

5F256CES

8

LFE3-17E-

6FN256CES

8

LFXP6C-

5F144CES

8

LFXP2-5E-

6F132CES

8

LFSC3GA15

E-5F256CES

8

Registers

Resource

Utilization

LUTs 2

sysMEM EBRs

2

2

1600-2100

1-2

1100-1400

1600-2200

1-2

1100-1400

1600-2200

1-2

1100-1400

1500-2100

1-2

1100-1400

1600-

2100

1-2

1100-

1400

1600-2200

1-2

1100-1400

1600-2200

1-2

1100-1400

Lattice ?

Implementation

Diamond ? 1.0 or ipLEVER ? 8.1

Design Tool

Support

Synthesis

Simulation

Synopsys ? Synplify ? Pro for Lattice D-2009.12L-1

Mentor Graphics ? Precision ? RTL

Aldec Active-HDL ? 8.1 Lattice Edition (Verilog and VHDL)

Mentor Graphics ? ModelSim ? 6.3f SE (Verilog only)

Cadence ? NC-Verilog ? (Linux only)

1) The SGMII Easy Connect option is only available on device families with SERDES I/O.

2) The leading number (before the dash) represents the TSMAC in Gigabit configuration option without the MIIM module. The lagging number

(after the dash) represents the TSMAC in Classic configuration option with MIIM module included. The numbers for SGMII Easy Connect

configuration option with MIIM modules are the same as the lagging numbers.

IPUG51_03.0, December 2010

5

Tri-Speed Ethernet MAC User’s Guide

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相关代理商/技术参数

TSMBG0505C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|100V V(BO) MAX|DO-215AA

TSMBG0506C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|110V V(BO) MAX|DO-214AA

TSMBG0507C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|145V V(BO) MAX|DO-214AA

TSMBG0509C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|185V V(BO) MAX|DO-215AA

TSMBG0510C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|200V V(BO) MAX|DO-214AA

TSMBG0511C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|210V V(BO) MAX|DO-214AA

TSMBG0512C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|215V V(BO) MAX|DO-214AA

TSMBG0514C 制造商:未知厂家制造商全称:未知厂家功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|250V V(BO) MAX|DO-214AA